BRUCE R. CHILDERS [pic], ASSOCIATE PROFESSORDepartment of Computer Science, University of PittsburghFaculty member of the Computer Engineering Program210 S. Bouquet St, Pittsburgh, PA 15260 USAPhone: 412-624-8421 (voice), 412-624-8854 (fax)E-mail: childers "at" cs.pitt.eduOffice: 6409 Sennott Square |
RESEARCH INTERESTS (Biography, CV)Compilers and software development tools, dynamic translation and virtual machines, computer architecture, and embedded and real-time systems. Continuous Compilation Research GroupPower-Aware Real-Time Systems GroupCustom Counterflow Pipelines for Embedded Processors |
RECENT PUBLICATIONS (Complete list)Transparent Debugging of Dynamically Optimized Code International Symposium on Code Generation and Optimization (CGO) Seattle, Washington , March 2009 Reducing Pressure in Bounded DBT Code Caches International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) Atlanta, Georgia , October 2008 Running a Java VM inside an Operating System Kernel: A Networking Case Study ACM International Conference on Virtual Execution Environments (VEE) Seattle, Washington , March 2008 Integrated CPU and Cache Power Management International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'08) Goteborg, Sweden , January 2008 Exploring the Interplay of Yield, Area and Performance in Processor Caches IEEE International Conference on Computer Design (ICCD) Lake Tahoe, CA , October 2007 Fragment Cache Management for Dynamic Binary Translators in Embedded Systems with Sratchpad International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) Salzburg, Austria , October 2007 Limits for a feasible speculative trace reuse implementation International Journal of High Performance Systems Architecture InderScience Publishers, 2007, Vol. 1, No. 1, pp. 69 - 76 Integrated CPU and L2 Cache Voltage Scaling using Machine Learning ACM Conference on Languages, Compilers, and Tools for Embedded Systems San Diego, California , June 2007 Virtual Execution Environments: Support and Tools Workshop on Next Generation Software, International Symposium on Parallel and Distributed Systems Long Beach, California , March 2007 (Invited) Energy Conservation using Power-Aware Cached-DRAM IEEE Transactions on Computers Accepted February 2007 Performance of Graceful Degradation for Cache Faults IEEE International Symposium on VLSI Porto Alegre, Brazil , May 2007 Integrated CPU and L2 Cache Frequency/Voltage Scaling using Supervised Learning HiPEAC Workshop on Statistical and Machine Learning Approaches Applied to Architectures and Compilation (SMART'07) Ghent, Belgium , January 2007 Evaluating Indirect Branch Handling Mechanisms in Software Dynamic Translation Systems ACM/IEEE International Symposium on Code Generation and Optimization (CGO) San Jose, California , March 2007 Power Aware Mapping of Real-Time Tasks to Multiprocessors The Handbook of Parallel Computing: Models, Algorithms, and Applications Edited by Sanguthevar Rajasekaran et al., CRC Press , 2006 A Speculative Trace Reuse Architecture with Reduced Hardware Requirements IEEE Int'l. Symp. on Computer Architecture and High Performance Computing (SBAC-PAD) Oureto, Brazil , October 2006 Catching and Identifying Bugs in Register Allocation 13th International Static Analysis Symposium Seoul, Korea , August 2006 Evaluating Fragment Creation Policies for SDT Systems 2nd Int'l. Conf. on Virtual Execution Environments Ottawa, Canada , June 2006 Profit-driven Scalar Optimization ACM Transactions on Architecture and Compiler Optimization Accepted May 2006, appeared in Vol. 3, Issue 3, pp. 231-262, September 2006 Power Management in External Memory using Power-Aware Cached-DRAM Int'l. Journal on Embedded Systems Accepted January 2006 Near-memory Caching for Improved Energy Consumption IEEE Int'l. Conf. on Computer Design (ICCD'05) San Jose, California , October 2005 TDB: A Source-Level Debugger for Dynamically Translated Programs ACM Sixth Int'l. Symp. on Automated and Analysis-Driven Debugging (AADEBUG'05) Monterey, California , September 2005. Planning for Code Buffer Management in Distributed Virtual Execution Environments ACM/USENIX Conference on Virtual Execution Environments (VEE'05) Chicago, Illinois , June 2005 Energy Conservation in Memory Hierarchies using Power-Aware Cached-DRAM Proceedings of the Schloss Dagstuhl Seminar on Power-Aware Computing Systems book chapter to be published by Springer-Verlag , June 2005. Collaborative Operating System and Compiler Power Management for Real-Time Applications ACM Transactions on Embedded Computing Systems Accepted April 2005. Compile-time planning for overhead reduction in software dynamic translators International Journal on Parallel Programming Vol. 33, No. 2-3, pp. 103-114 , Appeared June 2005 Jazz: A tool for demand-driven structural testing 14th ETAPS Int'l. Conf. on Compiler Construction (CC) Edinburgh, Scotland , April 2005 Demand-driven structural testing with dynamic instrumentation ACM SIGSOFT Int'l. Conf. on Software Engineering (ICSE'05) St. Louis, Missouri , May 2005 A Model-based Framework: An Approach to Profit-Driven Optimization ACM Int'l. Conf. on Code Generation and Optimization (CGO'05) San Jose, California , March 2005 |
UPCOMING CONFERENCESDagstuhl Seminar Emerging Uses and Paradigms for Binary Translation Schloss Dagstuhl, October 2008 International Symposium on Code Generation and Optimization Boston, Massachusetts, April 2008 11th Workshop on the Interaction between Compilers and Computer Architecture (INTERACT) Phoenix, Arizona, February 2007 Virtual Machines and Intermediate Languages for Emerging Modularization Mechanisms (VMIL) Vancouver, Canada, March 2007 7th International Symposium on Automated and Analysis-Driven Debugging (AADEBUG) Graz, Austria, April 2007 Int'l. Conf. on High Performance Embedded Architectures and Compilers (HiPEAC) Ghent, Belgium, January 2007 |
TEACHING |
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